A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM

In this article, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in the OFDM based IEEE 802.11a Wireless LAN (WLAN) baseband processor. The 64-point FFT is realized by decomposing it into a 2-D structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use any 2-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25 ?m BiCMOS technology. The core area of this chip is 6.8 mm2. The average dynamic power consumption is 41 mW @ 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i. e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption

A CORDIC like processor for computation of arctangent and absolute magnitude of a vector

In this paper, we propose a CORDIC like algorithm for computing absolute magnitude of a vector and its corresponding phase angle. It eliminates scale factor compensation step as well as the addition/subtraction operation along the z datapath. The synthesis result shows that the proposed processor is hardware economic and suitable for low power applications

Baseband processor for IEEE 802.11a standard with embedded BIST

In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally implementational results and power estimation are reported

A novel 64-point FFT/IFFT processor for IEEE 802.11(a) standard

A novel 64-point FFT/IFFT processor is presented in this article, named TURBO64, developed primarily for the application for the IEEE 802.11(a) standard. The processor does not use any digital multiplier or RAM. It has been fabricated and tested successfully. Its core area is 6.8 mm2 and the average power consumption is 41 mW at 1.8 V @ 20 MHz frequency. Compared to some other existing IP cores and ASIC chips TURBO64 needs a smaller number of clock cycles and consumes less power

A Low-Power 64-point FFT/IFFT Architecture for Wireless Broadband Communication

A low power 64-point FFT/IFFT architecture is developed for the application in OFDM based wireless broadband communication system. The proposed architecture satisfies the specifications of IEEE 802.11a and ETSI Bran. The architecture requires 25% multiplication and 86% addition/subtraction operation compared to the conventional Cooley-Tukey approach. This leads to power and area saving as well. The architecture is capable to perform FFT and IFFT without changing the internal coefficients which makes it highly suitable for practical applications

Implementation of an IEEE 802.11a compliant low-power baseband processor

Abstract – In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. Additionally, the design flow is briefly described and synthesis and layout results are reported

Base band processor for IEEE 802.11a standard with embedded BIST

In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally implementational results and power estimation are reported

Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronic